Address transition detection is typically used in asynchronous memories to detect when the address changes and to initiate a memory cycle. During a full memory cycle a number of activities, such as word line enable, bit line precharge, and sense amplifier enable, are performed. In one memory access, the contents of memory cells in a specific row as indicated by the row address are read, and final output from the memory are a subset of the accessed data as specified by the column address. In certain asynchronous memories, a low power fast access mode is made possible by distinguishing row address changes from column address changes, where a memory array access is initiated only when the row address changes.
It is desirable to apply the same technique to synchronous memories which uses a clock signal. However, some difficulties need to be overcome in order to do so. First, in synchronous memories, the address is required to be valid only at selected portions of the clock cycle. Thus it is imperative to distinguish address transitions from one valid address to the next valid address, allowing for possible transitions therebetween. Second, since some synchronous memories derive a performance benefit from initiating activities upon a clock edge, delaying such initiation to distinguish an address transition could cause an undesirable increase in access time.
Thus there is a need for synchronous memories incorporating address transition detection. There is a further need for synchronous memories incorporating address transition detection that allows for instances in the clock cycle during which address is not valid. Additionally, it is advantageous to incorporate the address transition detection without delaying access time.